1. Field of the Invention
The present invention relates to an output buffer circuit for a semiconductor device, and in particular to an output buffer circuit capable of improving an output speed.
2. Description of the Conventional Art
FIG. 1 is a block diagram of a conventional output buffer circuit including an output control circuit 10, and inverters 11, 12, each of which is composed of a plurality of NMOS transistors.
The operation of the conventional output buffer circuit will now be described.
When the inverters 11, 12 respectively receive clock signals NU1, NU2 of a high level and clock signals ND1, ND2 of a low level, which are outputted from the output control circuit 10, the inverters 11, 12 output data signals at a high level, and when the inverters 11, 12 respectively receive clock signals NU1, NU2 at a low level and clock signals ND1, ND2 at a high level, the inverters 11, 12 output data signals at a low level.
Here, the clock signals NU1, NU2 for outputting the data signals at the high level have different roles from each other.
That is, the clock signal NU1 is applied to obtaining prompt data output, and the clock signal NU2, a delayed signal compared with the clock signal NU1, serves as a signal which maintains output of a data signal at a high level, and improves the output speed by reducing the instantaneous peak current I.sub.PC, which is generated when the output is at a high level, as shown in FIG. 2, and therefore for reducing noise due to the peak current I.sub.PC.
The conventional output buffer circuit maintains the high level data output which is the high level at a VCC-Vth level by employing pull-up NMOS transistors NM1, NM2, thereby reducing the amount by which the data out is charged at the high level and reducing the noise generated when the data output is transited from the high level to the low level.
However, in the conventional output buffer circuit, the output level is limited to the VCC-Vth level due to using the NMOS transistors. Therefore, when the VCC level is increased by .DELTA.v, the output level is also increased by .DELTA.V. In result, the output level is increased in accordance with an increase in VCC, thus increasing the noise and therefore slowing down the output speed.